In sub-micron Complimentary Metal-Oxide Semiconductor (CMOS) manufacturing self-aligned contact (SAC) technology has been successfully used to achieve chip size reduction. In conventional SAC processes structures that are to be connected with overlying layers using a self-aligned contact are closely spaced on the semiconductor substrate. A silicon nitride barrier layer is formed over the structure that is to be contacted. A pre-metal dielectric film of oxide or doped oxide is then deposited over the barrier layer. A selective etch is then performed to form contact openings that extend through the pre-metal dielectric layer. This etch stops on the barrier layer. The exposed portions of the barrier layer are then removed, exposing the structure that is to be contacted. A metal layer is then deposited and planarized to complete the self-aligned contact. The etch stop layer prevents over-etch, aligning the contact with the structure to be contacted and preventing current leakage that could result from improper alignment.
SAC processes allow for the formation of closely spaced structures, giving high density semiconductor devices. However, the speed of devices formed with SAC processes is significantly less than the speed of devices formed with non-SAC processes. Accordingly, there is a need for CMOS devices that have both high density and high speed. Also, there is a need for a process for forming CMOS devices that have both high density and high speed. The present invention meets the above needs.